3. Fetch

The fetch operation is responsible for getting an instruction or data from main memory into the CPU.

Note that there can be many programs loaded in memory at the same time and each one will have a unique starting address.

Programs do not necessarily start at location zero. Let's look at a program that begins at location 305 in main memory.

The table below shows the situation at the start of the fetch cycle, with the program counter (in the CPU) pointing to location 305 in RAM. As this is a new program let's assume that the accumulator is set to zero. Note that if the program had already been running for a while the accumulator would most likely contain a different value.

The Program Counter has been pre-loaded with the starting address of the first instruction within the program which in this case is 305.

During the first stage of the fetch cycle, the program counter value is copied into the Memory Address Register (MAR). See below

Once the MAR is loaded, the Control Unit loads the address (305) on to the address bus and also sends a signal to main memory to read the instruction contained at that address.

As you can see in the diagram above, location 305 in RAM contains an instruction 'add #5'.

Now the instruction is passed across the data bus and copied into the Memory Data Register. See below

Then the instruction in the MDR is copied into the Instruction Register so that it is ready to use during the next stage (decode)

The program counter is now incremented by one location, changing it to 306 so that it is ready to begin the next fetch cycle.

This is the end of the fetch cycle.